puts "Start to source [info script]"
global SLR0_DPU_V3_TOP   
set_property LOC RAMB36_X0Y0  [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[0].ram_18_0_6_b0.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X0Y4  [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[1].ram_18_0_6_b0.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X0Y8  [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[2].ram_18_0_6_b0.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X0Y12 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[3].ram_18_0_6_b0.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X0Y16 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[4].ram_18_0_6_b0.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X0Y20 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[5].ram_18_0_6_b0.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X0Y24 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[6].ram_18_0_6_b0.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X0Y28 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[7].ram_18_7_13_b0.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X0Y32 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[8].ram_18_7_13_b0.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X0Y36 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[9].ram_18_7_13_b0.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X0Y40 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[10].ram_18_7_13_b0.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X0Y44 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[11].ram_18_7_13_b0.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X0Y48 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[12].ram_18_7_13_b0.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X0Y52 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[13].ram_18_7_13_b0.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X0Y56 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[14].ram_18_14_b0.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
## ===========================================
set_property LOC RAMB36_X1Y0  [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[15].ram_18_15_21_b1.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X1Y4  [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[16].ram_18_15_21_b1.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X1Y8  [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[17].ram_18_15_21_b1.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X1Y12 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[18].ram_18_15_21_b1.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X1Y16 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[19].ram_18_15_21_b1.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X1Y20 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[20].ram_18_15_21_b1.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X1Y24 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[21].ram_18_15_21_b1.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X1Y28 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[22].ram_18_22_28_b1.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X1Y32 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[23].ram_18_22_28_b1.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X1Y36 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[24].ram_18_22_28_b1.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X1Y40 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[25].ram_18_22_28_b1.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X1Y44 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[26].ram_18_22_28_b1.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X1Y48 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[27].ram_18_22_28_b1.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X1Y52 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[28].ram_18_22_28_b1.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X1Y56 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[29].ram_18_29_b1.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
## ===========================================
set_property LOC RAMB36_X2Y0  [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[30].ram_18_30_36_b2.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X2Y4  [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[31].ram_18_30_36_b2.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X2Y8  [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[32].ram_18_30_36_b2.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X2Y12 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[33].ram_18_30_36_b2.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X2Y16 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[34].ram_18_30_36_b2.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X2Y20 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[35].ram_18_30_36_b2.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X2Y24 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[36].ram_18_30_36_b2.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X2Y28 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[37].ram_18_37_43_b2.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X2Y32 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[38].ram_18_37_43_b2.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X2Y36 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[39].ram_18_37_43_b2.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X2Y40 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[40].ram_18_37_43_b2.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X2Y44 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[41].ram_18_37_43_b2.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X2Y48 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[42].ram_18_37_43_b2.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X2Y52 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[43].ram_18_37_43_b2.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X2Y56 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[44].ram_18_44_b2.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
## ===========================================
set_property LOC RAMB36_X3Y0  [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[45].ram_18_45_51_b3.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X3Y4  [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[46].ram_18_45_51_b3.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X3Y8  [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[47].ram_18_45_51_b3.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X3Y12 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[48].ram_18_45_51_b3.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X3Y16 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[49].ram_18_45_51_b3.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X3Y20 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[50].ram_18_45_51_b3.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X3Y24 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[51].ram_18_45_51_b3.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X3Y28 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[52].ram_18_52_58_b3.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X3Y32 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[53].ram_18_52_58_b3.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X3Y36 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[54].ram_18_52_58_b3.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X3Y40 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[55].ram_18_52_58_b3.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X3Y44 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[56].ram_18_52_58_b3.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X3Y48 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[57].ram_18_52_58_b3.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X3Y52 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[58].ram_18_52_58_b3.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X3Y56 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[59].ram_18_59_b3.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
## ===========================================
set_property LOC RAMB36_X5Y0  [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[60].ram_18_60_66_b4.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X5Y4  [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[61].ram_18_60_66_b4.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X5Y8  [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[62].ram_18_60_66_b4.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X5Y12 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[63].ram_18_60_66_b4.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X5Y16 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[64].ram_18_60_66_b4.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X5Y20 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[65].ram_18_60_66_b4.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X5Y24 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[66].ram_18_60_66_b4.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X5Y28 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[67].ram_18_67_73_b4.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X5Y32 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[68].ram_18_67_73_b4.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X5Y36 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[69].ram_18_67_73_b4.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X5Y40 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[70].ram_18_67_73_b4.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X5Y44 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[71].ram_18_67_73_b4.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X5Y48 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[72].ram_18_67_73_b4.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X5Y52 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[73].ram_18_67_73_b4.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X5Y56 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[74].ram_18_74_b4.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
## ===========================================
set_property LOC RAMB36_X6Y0  [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[75].ram_18_75_81_b5.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X6Y4  [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[76].ram_18_75_81_b5.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X6Y8  [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[77].ram_18_75_81_b5.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X6Y12 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[78].ram_18_75_81_b5.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X6Y16 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[79].ram_18_75_81_b5.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X6Y20 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[80].ram_18_75_81_b5.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X6Y24 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[81].ram_18_75_81_b5.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X6Y28 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[82].ram_18_82_88_b5.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X6Y32 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[83].ram_18_82_88_b5.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X6Y36 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[84].ram_18_82_88_b5.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X6Y40 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[85].ram_18_82_88_b5.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X6Y44 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[86].ram_18_82_88_b5.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X6Y48 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[87].ram_18_82_88_b5.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X6Y52 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[88].ram_18_82_88_b5.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X6Y56 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[89].ram_18_89_b5.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
## ===========================================
set_property LOC RAMB36_X7Y0  [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[90].ram_18_90_96_b6.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X7Y4  [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[91].ram_18_90_96_b6.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X7Y8  [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[92].ram_18_90_96_b6.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X7Y12 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[93].ram_18_90_96_b6.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X7Y16 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[94].ram_18_90_96_b6.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X7Y20 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[95].ram_18_90_96_b6.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X7Y24 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[96].ram_18_90_96_b6.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X7Y28 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[97].ram_18_97_103_b6.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X7Y32 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[98].ram_18_97_103_b6.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X7Y36 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[99].ram_18_97_103_b6.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X7Y40 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[100].ram_18_97_103_b6.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X7Y44 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[101].ram_18_97_103_b6.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X7Y48 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[102].ram_18_97_103_b6.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X7Y52 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[103].ram_18_97_103_b6.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X7Y56 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[104].ram_18_104_b6.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
## ===========================================
set_property LOC RAMB36_X8Y0  [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[105].ram_18_105_111_b7.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X8Y4  [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[106].ram_18_105_111_b7.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X8Y8  [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[107].ram_18_105_111_b7.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X8Y12 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[108].ram_18_105_111_b7.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X8Y16 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[109].ram_18_105_111_b7.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X8Y20 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[110].ram_18_105_111_b7.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X8Y24 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[111].ram_18_105_111_b7.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X8Y28 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[112].ram_18_112_118_b7.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X8Y32 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[113].ram_18_112_118_b7.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X8Y36 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[114].ram_18_112_118_b7.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X8Y40 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[115].ram_18_112_118_b7.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X8Y44 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[116].ram_18_112_118_b7.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X8Y48 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[117].ram_18_112_118_b7.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X8Y52 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[118].ram_18_112_118_b7.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
set_property LOC RAMB36_X8Y56 [get_cells $SLR0_DPU_V3_TOP/u_wbuf/bram_sdp_2048b_8k/gen_rams[119].ram_18_119_b7.u_buf_ram_18bx8k_1r1w1c_w_i/gen_brams[0].gen_brams_first.RAMB36E2_ins]
